DARPA asks industry for SWaP-optimized machine learning real-time ASICs able to learn from data | Military Aerospace
EETimes - Eta's Ultra Low-Power Machine Learning Platform
Arch-Net: A Family Of Neural Networks Built With Operators To Bridge The Gap Between Computer Architecture of ASIC Chips And Neural Network Model Architectures - MarkTechPost
Machine Learning in Energy - ADG Efficiency
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
ASIC Design Services | Microsemi
FPGA Based Deep Learning Accelerators Take on ASICs
Easing the Effort: Mipsology Accelerates ML with Zebra FPGA IP - News
How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices - Blog - Company - Aldec
Google AI Blog: Chip Design with Deep Reinforcement Learning
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
The Definitive Guide to Deep Learning with GPUs | cnvrg.io
My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
Intel Speeds AI Development, Deployment and Performance with New Class of AI Hardware from Cloud to Edge | Business Wire
Deep Learning Has Hit a Wall, Intel's Rao Says
Are ASIC Chips The Future of AI?
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
FPGA Based Deep Learning Accelerators Take on ASICs
